Direct Memory Access (DMA) is commonly used in modern computing systems to permit hardware subsystems to access system memory independently of a central processing unit (CPU). Hardware subsystems utilizing DMA may include disk drive controllers, graphics cards, network cards, sound cards, and the like. Utilizing DMA permits a system to transfer data to and from these devices with much less CPU overhead. By using DMA to directly access these hardware subsystems, the CPU is removed from the copy and transfer of data from the host to target devices.
In a conventional computing system, a CPU may initiate a transfer with a command given by firmware to a DMA engine, though the CPU does not execute the command. The firmware command may include the host address to access and a byte count. The DMA engine then requests the information or executes the command to the host device. The DMA engine may also assign a transaction identification (TID) to each interaction with the host device. The TID is assigned to track the requests from the DMA engine. Once an operation is complete, the TID is returned to a pool of available TIDs. If an operation is not completed, for example, when the operation times out because of a non-responsive device, the associated TID is retired. Because the TID is retired, the operation will no longer be associated with that command. If there are later returns of that command, it will not cause any mismatch. As more TIDs are retired, there are fewer permissible transactions occurring at a given time. Therefore, the TIDs should be reset periodically when the available TIDs affect system performance. However, conventionally, all DMA requests must be completed before resetting the TIDs. Therefore, the system operations must be suspended in order to reset the TIDs, which costs system time and performance.
In conventional DMA engines, the process of restoring retired TIDs requires all DMA activities to quiet or complete, for all channels. Firmware can ensure that all outstanding DMA requests are completed. The restore action generally acts like a TID first in, first out (FIFO) reset. Any outstanding DMA requests with a particular TID would be skewed during the TID FIFO reset. There may be a performance cost associated with the reset, and the DMA engines for the various channels that do not retire any TIDs may be affected. In addition, firmware complexity may be increased due to the coordination between multiple processors. Finally, during a restore TID operation, firmware cannot issue any more DMA commands, and the wait for outstanding DMA commands to complete may be unpredictable, depending on the host latency and other traffic on the system.